A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
复制标题
用于估算 CMOS 逻辑门最小工作电压 (VDDmin) 的封闭式表达式
DOI：
10.1145/2024724.2024942
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
T. Sakurai
中科院分区：
文献类型：
--
作者：
H. Fuketa;S. Iida;Tadashi Yasufuku;M. Takamiya;M. Nomura;H. Shinohara;T. Sakurai
在本文中，提出了一种用于估计 CMOS 逻辑门的最小工作电压（VDDmin）的封闭式表达式。 VDDmin 被定义为电路可以正常工作的最小电源电压。组合电路的VDDmin可以写为逻辑门数量的对数平方根的线性函数，其斜率与PMOS和NMOS晶体管之间的阈值电压差的管芯内变化的标准偏差成正比。使用各种门链通过蒙特卡罗模拟验证了所提出的表达式。验证表明，逆变器链的 VDDmin 可以估计到 11% 的误差范围内。该表达式还通过 65nm CMOS 工艺中的硅测量进行了验证
In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process