Tag compression for low power in dynamically customizable embedded processors
Tag compression for low power in dynamically customizable embedded processors
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标签压缩可在动态可定制的嵌入式处理器中实现低功耗
DOI：
10.1109/tcad.2004.829823
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发表时间：
2004
影响因子：
2.9
通讯作者：
A. Orailoglu
中科院分区：
文献类型：
--
作者：
Peter Petrov;A. Orailoglu
针对低功耗嵌入式处理器，提出了一种基于指令/数据缓存标签压缩的功耗降低方法。通过静态分析应用热点的代码/数据存储布局，可以采用各种有效减小标签大小的方案来最小化指令和数据高速缓存中的功率。该方案依赖于显著减少存储在用于高速缓存冲突识别的标签阵列中的标签位的数量，从而显著减少有效位线、读出放大器和比较器单元的数量。我们提出了一组标签压缩技术，并从效率和所需的硬件支持两个方面分别对每种技术进行了评估。对每种技术进行了详细的超大规模集成实现，并报告了在一组嵌入式应用程序上的一些实验结果。可以观察到标签阵列的能量消耗降低高达95%，这意味着当在整个高速缓冲存储器子系统中摊销时，能量显著降低50%的范围。
We present a methodology for power reduction by instruction/data cache-tag compression for low-power embedded processors. By statically analyzing the code/data memory layouts for the application hot spots, a variety of proposed schemes for effective tag-size reduction can be employed for power minimization in instruction and data caches. The schemes rely on significantly reducing the number of tag bits stored in the tag arrays for cache-conflict identification, thus considerably decreasing the number of active bitlines, sense amps, and comparator cells. We present a set of tag compression techniques and evaluate each of them separately in terms of efficiency and required hardware support. A detailed very large scale integrated implementation has been performed and a number of experimental results on a set of embedded applications is reported for each technique. Energy dissipation decreases of up to 95% can be observed for the tag arrays, implying significant energy reductions in the range of 50% when amortized across the overall cache subsystem.