Fully parallel integrated CAM/RAM using preclassification to enable large capacities
Fully parallel integrated CAM/RAM using preclassification to enable large capacities
复制标题
使用预分类实现大容量的完全并行集成 CAM/RAM
DOI：
10.1109/4.509851
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
P. G. Gulak
中科院分区：
文献类型：
--
作者：
K. J. Schultz;P. G. Gulak
许多应用程序将受益于大容量内容可寻址存储器（CAM）的可用性。然而，虽然RAM、EEPROM和其他存储器类型实现了不断增加的每芯片位计数，但CAM几乎没有希望效仿，这主要是由于实现二维解码的固有困难。在速度敏感的环境中，大多数建议的解决方案的串行化操作是不可接受的。在响应所产生的需要，本文介绍了一种完全并行（单时钟周期）CAM架构，使用的概念，“预分类”，以实现第二维解码，而不影响吞吐量。通常情况下，每个CAM条目用作RAM中附加数据的索引。为了实现改进的系统集成，预分类的CAM被合并到与其目标RAM相同的物理阵列中，并且两者使用相同的核心单元。所产生的新型存储器的架构和操作进行了描述，是两个关键路径电路：匹配线下拉和多匹配解析器。的存储器电路，设计在0.8 /spl μ/m BiCMOS技术，可以采用在芯片大至1 Mb，和模拟确认37 MHz的操作，这个容量。为了实验验证的架构和电路设计的可行性，一个8 kb的测试芯片被制造，并发现是完全功能的时钟速度高达59 MHz，在50 MHz的功耗为260 mW。
Many applications would benefit from the availability of large-capacity content addressable memories (CAMs). However, while RAMs, EEPROMs, and other memory types achieve ever-increasing per-chip bit counts, CAMs show little promise of following suit, due primarily to an inherent difficulty in implementing two-dimensional decoding. The serialized operation of most proposed solutions is not acceptable in speed-sensitive environments. In response to the resulting need, this paper describes a fully-parallel (single-clock-cycle) CAM architecture that uses the concept of "preclassification" to realize a second dimension of decoding without compromising throughput. As is typically the case, each CAM entry is used as an index to additional data in a RAM. To achieve improved system integration, the preclassified CAM is merged into the same physical array as its target RAM, and both use the same core cells. Architecture and operation of the resulting novel memory are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. The memory circuits, designed in 0.8 /spl mu/m BiCMOS technology, may be employed in chips as large as 1 Mb, and simulations confirm 37 MHz operation for this capacity. To experimentally verify the feasibility of the architectural and circuit design, an 8 kb test chip was fabricated and found to be fully functional at clock speeds up to 59 MHz, with a power dissipation of 260 mW at 50 MHz.