PCAsim: A parallel cycle accurate simulation platform for CMPs
PCAsim: A parallel cycle accurate simulation platform for CMPs
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PCAsim：用于 CMP 的并行周期精确仿真平台
DOI：
10.1109/iccda.2010.5540881
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Zhe Gong
中科院分区：
文献类型：
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作者：
Xiaodong Zhu;Junmin Wu;Xiufeng Sui;Wei Yin;Qingbo Wang;Zhe Gong
随着多核时代的到来，芯片多处理器（CMP）架构提出了一个挑战，有效的仿真，结合一个详细的模拟器运行现实的工作负载的要求。并行化是一种常用的减少CMP仿真时间的方法，它可以充分利用CMP仿真中固有的并行性。我们设计并实现了PCAsim，一个运行在共享内存平台上的并行周期精确和用户级的CMP模拟器。模拟器是并行的POSIX线程根据目标系统架构。每个核心线程和管理器线程都与Slack机制同步[11]。但我们发现松弛机制不能保证模拟器对网络活动和缓存一致性协议产生的事件的时间违规。为了解决这个问题，我们提出了一个有效的同步方法称为挂起屏障。该方法增强了传统的保守并行同步机制的能力，在性能损失很小的情况下提高了仿真精度。在实现PCAsim的过程中，除了同步问题，我们还遇到了许多其他棘手的问题。本文描述了一些常见的问题，并说明了我们如何解决这些问题。测试结果表明，PCAsim算法具有较好的加速性能和可扩展性。
As the approaching of the multi-core era, chip multiprocessor(CMP) architectures present a challenge for efficient simulation, combining with the requirements of a detailed simulator running realistic workloads. Parallelization, which can exploit inherent parallelism in CMP simulation, is a common method to reduce simualtion time. We design and implement PCAsim, a parallel cycle accurate and user-level CMP simulator running on shared memory platform. The simulator is parallelized by POSIX threads according to target system architecture. Each core thread and the manager thread are synchronized with Slack mechanism [11]. But we find slack mechanism can not ensure the simulator against time violation among events generated by network activity and cache coherence protocol. To solve the problem, we propose an effective synchronous method called pending barrier. This method augments the power of traditional conservative parallel synchronous mechanism and improves simulation accuracy with negligible performance degradation. Except synchronization, we also encountered many other troublesome issues in implementing PCAsim. This paper describes some common ones and illustrates how we address them. The evaluations show that PCAsim can achieve reasonable speed-up and scalability.