Testing SoC interconnects for signal integrity using extended JTAG architecture
Testing SoC interconnects for signal integrity using extended JTAG architecture
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使用扩展 JTAG 架构测试 SoC 互连的信号完整性
DOI：
10.1109/tcad.2004.826540
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发表时间：
2004
影响因子：
2.9
通讯作者：
M. Nourani
中科院分区：
文献类型：
--
作者：
M. Tehranipour;N. Ahmed;M. Nourani
随着技术的缩小和工作频率达到多层型范围，设计和测试互连不再是微不足道的问题。在本文中，我们提出了一个增强的边界扫描架构，以测试高速互连的信号完整性。该体系结构包括：1）根据多个过渡模型以及2）监视信号完整性违规的观察单元。为了完全符合常规的关节测试组标准，使用两个新的说明来控制单元格和扫描活动，以完整性测试模式进行扫描。
As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.