Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching
Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching
复制标题
用于高效网络入侵检测模式匹配的移位或电路
DOI：
10.1109/fpl.2006.311314
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
D. Lo
中科院分区：
文献类型：
--
作者：
Huang;Wen;D. Lo
介绍了一种新型的基于现场可编程门阵列的签名匹配协处理器体系结构，作为基于硬件的网络入侵检测系统的核心。签名匹配协处理器结构基于移位或算法。该体系结构由简单的移位寄存器、或门和存储模式的只读存储器组成。实验结果表明，与相关工作相比，该方法在网络入侵检测系统的FPGA实现中获得了更高的吞吐量和更少的硬件资源
This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardware-based network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems