Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis

Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis
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DOI:
10.7873/date.2013.323
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发表时间:
2013-03
期刊:
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)
影响因子:
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通讯作者:
L. Ramini;P. Grani;S. Bartolini;D. Bertozzi
L. Ramini;P. Grani;S. Bartolini;D. Bertozzi
中科院分区:
其他
文献类型:
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作者:
L. Ramini;P. Grani;S. Bartolini;D. Bertozzi

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光片上网络(ONoCs)目前仍处于概念阶段,并且将受益于能够弥合抽象分析框架与物理层所带来的约束和挑战之间的差距的探索性研究。本文的目的是超越传统的比较波长路由的ONoC拓扑结构的基础上,仅根据其抽象的属性,并首次评估其物理实现效率在一个同质的实验设置的实际意义。结果表明,在目标系统布局约束的影响下,拓扑布局与其逻辑方案之间存在着显著的、不同的偏差。这将成为准确表征特定技术指标(如插入损耗关键路径)的第一步,并得出对每个设计的功率效率和可行性的最终影响。
Optical networks-on-chip (ONoCs) are currently still in the concept stage, and would benefit from explorative studies capable of bridging the gap between abstract analysis frameworks and the constraints and challenges posed by the physical layer. This paper aims to go beyond the traditional comparison of wavelength-routed ONoC topologies based only on their abstract properties, and for the first time assesses their physical implementation efficiency in an homogeneous experimental setting of practical relevance. As a result, the paper can demonstrate the significant and different deviation of topology layouts from their logic schemes under the effect of placement constraints on the target system. This becomes then the preliminary step for the accurate characterization of technology-specific metrics such as the insertion loss critical path, and to derive the ultimate impact on power efficiency and feasibility of each design.