Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits
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DOI：
10.1109/jssc.2003.820873
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发表时间：
2004-01-01
影响因子：
5.4
通讯作者：
Tuinhout, HP
中科院分区：
文献类型：
--
作者：
de Gyvez, JP;Tuinhout, HP
由于当前和未来深亚微米CMOS技术的器件和电压缩放方案，MOSFET晶体管的关态电流（I-off）不可避免地随着技术最小尺寸的缩小而增加。实验证据表明，现代深亚微米设计的漏电流分布不仅具有更高的平均值，而且还呈现出更大的可变性。在本文中，我们调查的影响，阈值电压失配作为一个合理的来源，这种增加的变化。在数字电路设计中，通常假设静态CMOS单元的阈值电压差（失配）可以忽略不计。然而，阈值电压失配（Δ V（to））对软态电流具有双侧影响。也就是说，总单元的电流可以根据V-t失配偏移的方向而增加或减少。这种影响可能非常严重，以至于I-off可以增加一个以上的数量级。仅由于V-to失配，其幅值相对于其标称值。我们进一步表明，通过实验结果的V-到失配的配对的晶体管工作在亚阈值制度相比，工作在饱和或线性区域的晶体管可以更糟的两个因素。如果期望获得与在亚阈值范围之外表征的V到失配相同的I-off电平，则在面积、速度和功耗方面，较大扩展的两倍显然是相当破坏性的。
Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I-off) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern, deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (DeltaV(to)) has a two-sided effect on the oft-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V-t mismatch shift. This effect can be so severe that I-off can increase by more than one order of. magnitude with, respect to its nominal value due only to V-to mismatch. We further show through experimental results that the V-to mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I-off level as for a V-to mismatch characterized out of the subthreshold regime.