2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products
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2.2 适用于高性能服务器和桌面产品的 AMD Chiplet 架构
DOI：
10.1109/isscc19947.2020.9063103
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
M. Subramony
中科院分区：
文献类型：
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作者：
S. Naffziger;Kevin M. Lepak;Milam Paraschou;M. Subramony
AMO的“罗马”和“Matisse”是第二代AMD Infinity Fabric-based SoC，采用3种独特的混合工艺技术芯片，分别针对服务器和客户端市场实现领先的性能、性能/美元和性能/瓦（图2.2.1）。小芯片架构可为多个市场提供领先的7纳米[1] CPU，同时在可扩展设计中保留对复杂10和内存子系统的向后兼容性，具有高度重用性，以缩短上市时间。一个关键的好处是在CPU和10/mixed-signaIP之间部署的异构技术。众所周知，模拟电路的高级节点中的收缩因子比数字逻辑和SRAM低得多。通过将存储器接口和系列保持在成熟的12纳米技术中，成本得以降低，因为这些电路的收缩系数非常小，仅为7纳米，并且高级节点的性能或功耗增益非常小。低成本的12纳米10芯片（IOD）与高产量的8“Zen 2”内核、74 mm 2 7纳米CPU计算芯片（CCD）联合收割机相结合，提供了非常经济高效的性能。
AMO's “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targeting server and client markets, respectively (Fig. 2.2.1). The chiplet architecture enables leading edge 7nm [1] CPUs for multiple markets, while retaining backward compatibility to complex 10 and memory subsystems in a scalable design with high reuse for improved time-to-market. A key benefit is the heterogeneous technology deployed between the CPUs and the 10/mixed-signaIP. It is well known that shrink factors in advanced nodes are much lower for analog circuitry than for digital logic and SRAM. By keeping the memory interfaces and SerOes in mature 12nm technology, costs are mitigated since those circuits see a very small shrink factor to 7nm and very little performance or power gain from advanced nodes. A low-cost 12nm 10 die (IOD) with the high-yielding 8 “Zen2” core, 74mm2 7nm CPU compute die (CCD) combine to provide very cost-effective performance.