Test wrapper and test access mechanism co-optimization for system-on-chip
Test wrapper and test access mechanism co-optimization for system-on-chip
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DOI：
10.1023/a:1014916913577
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发表时间：
2002-04-01
影响因子：
0.9
通讯作者：
Marinissen, EJ
中科院分区：
文献类型：
--
作者：
Iyengar, V;Chakrabarty, K;Marinissen, EJ
测试访问机制（TAM）和测试包装器是片上系统SOC测试架构的组成部分。先前的研究一次只集中在TAM/包装器设计问题的一个方面，即，或者为一组预先设计的包装器优化TAM，或者为给定TAM宽度优化包装器。在本文中，我们解决了一个更普遍的问题，即进行TAM设计和包装优化结合起来。我们提出了一个有效的算法来构造包装器，减少测试时间的核心。我们的包装器设计算法改进了早期的方法，也减少了TAM的宽度，以实现这些较低的测试时间。我们提出了新的TAM优化的数学模型，使用我们的包装设计算法计算的核心测试时间值。我们进一步提出了一个新的枚举方法TAM优化，减少执行时间显着时，被设计的TAM的数量是小的。一个学术SOC以及工业SOC的实验结果。
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.