Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics
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使用 iso-metrics 评估非对称多核片上系统的容错能力

DOI:
10.1049/iet-cdt.2015.0056
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发表时间:
2016
影响因子:
1.2
通讯作者:
Chalios C
Chalios C
中科院分区:
计算机科学4区
文献类型:
--
作者:
Chalios C

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Dennard缩放的结束将低功耗提升为计算系统的一阶关注点。然而,在性能受限的环境中使用时,电压和频率缩放等传统节能方案正达到其极限。需要新技术来打破功率墙,同时保持未来处理器的性能。低功耗嵌入式处理器和近阈值电压计算(NTVC)已被提出作为解决未来计算系统中的功率墙的可行解决方案。不幸的是,这些技术也可能会损害每核心性能,并且在NTVC的情况下,可靠性。这些限制使它们不适合HPC系统和嵌入式系统。为了证明新兴的低功耗处理技术可以有效地取代传统技术,本研究依赖于ARM的big.LITTLE处理器作为实际和仿真平台,以及CG求解器的最新实现。特别是对于NTVC,该研究描述了高效的基于算法的容错方案如何保持极低电压操作的功率和能量优势。
The end of Dennard scaling has promoted low power consumption into a first‐order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance‐constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low‐power embedded processors and near‐threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per‐core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low‐power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state‐of‐the‐art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm‐based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.
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