A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip
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DOI:
10.1109/jssc.2023.3283961
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发表时间:
2024-02
影响因子:
5.4
通讯作者:
Chuxiong Lin;Weifeng He;Yanan Sun;Lin Shao;Bo Zhang;Jun Yang;Mingoo Seok
Chuxiong Lin;Weifeng He;Yanan Sun;Lin Shao;Bo Zhang;Jun Yang;Mingoo Seok
中科院分区:
工程技术1区
文献类型:
--
作者:
Chuxiong Lin;Weifeng He;Yanan Sun;Lin Shao;Bo Zhang;Jun Yang;Mingoo Seok

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对于具有多个电压/频率域的片上网络(NoC),亚稳态损害了时钟域交叉期间的可靠性,特别是在近阈值电压(NTV)区域。传统的多级同步器降低了亚稳定性的概率,但具有高延迟代价。本文提出了一种名为亚稳态风险预测和缓解(MPAM)的技术,该技术通过三相时钟监控电路预测不久的将来的亚稳态风险,并通过无亚稳态时钟方案来缓解这些风险。因此,MPAM仅启用一个触发器用于数据同步,而不会降低针对亚稳态的可靠性,从而改善了NoC的延迟和吞吐量。我们在40 nm低功耗(LP)工艺中制作了一个2 × 2 NoC测试芯片的原型,该芯片具有四个独立的电压/频率域,并采用了MPAM技术。测量结果表明,在不同的时钟频率比下,MPAM使亚稳态条件率降低了10 ^{10}$倍。此外,通过仅启用一个触发器进行同步,基于MPAM的NoC实现了分组延迟减少,吞吐量提高和能源效率分别提高了58%,13.4%和8.6%。
For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the reliability during the clock-domain crossing, especially in the near-threshold-voltage (NTV) region. Conventional multistage synchronizers reduce the probability of metastability but have a high latency penalty. This article presents a technique titled metastability risk prediction and mitigation (MPAM) that predicts the near-future metastability risks by a triple-phase clock monitoring circuitry and mitigates them by a metastability-free clock scheme. Therefore, the MPAM enables only one flip-flop for data synchronization without degrading the reliability against metastability, thus improving the latency and throughput of NoC. We prototyped a 2-by-2 NoC test chip with four independent voltage/frequency domains in a 40-nm low-power (LP) process, featuring the MPAM technique. The measurement shows that the MPAM significantly reduces the metastability condition rate by $10^{10}$ times under different clock frequency ratios. Moreover, by enabling only one flip-flop for synchronization, the MPAM-based NoC achieves packet latency reduction, throughput improvement, and energy efficiency gain by 58%, 13.4%, and 8.6%, respectively.