Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
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DOI：
10.1109/arith48897.2020.00019
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发表时间：
2020-06
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通讯作者：
Mojtaba Bisheh-Niasar;R. Khatib;R. Azarderakhsh;Mehran Mozaffari Kermani
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作者：
Mojtaba Bisheh-Niasar;R. Khatib;R. Azarderakhsh;Mehran Mozaffari Kermani
本文演示了椭圆曲线密码（ECC）的快速和紧凑的实现，在曲线25519高效的密钥协商。Curve 25519最近已被采用作为几个应用程序的密钥交换方法，并被纳入美国国家标准与技术研究所（NIST）的公钥密码学建议。本文提出了三种不同的性能水平的设计，包括轻量级的，面积时间有效的，高性能的架构。轻量级硬件实现用于几个物联网（IoT）应用程序，因为它们的资源非常宝贵。我们的轻量级架构利用90%的资源相比，最好的以前的工作，而它仍然是更优化的方面A middot; T（面积×时间）。为了从时间或利用的资源有效地实现，我们的面积时间高效的架构可以建立每秒近7,000个关键会话，比以前的作品快64%。面积时间有效的架构使用良好的调度交织乘法结合减少算法。此外，我们还提供了一个基于4级Karatsuba方法和Carry-Compact Addition（CCA）的高性能应用程序的快速架构。我们的高性能架构也优于以前的工作方面的A middot; T。结果显示A middot; T和Ad middot; T（DSP_count×时间）分别改善9%和29%。所有架构都是在Xilinx Zynq-7020 FPGA系列上实现的可变基点，其中报告和比较了性能和实现指标。最后，各种侧信道攻击对策嵌入在所提出的架构。
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90% less resources compared to the best previous work while it is still more optimized in term of A middot; T (area×time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9% and 29% improvement in A middot; T and Ad middot; T (DSP_count×time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.