Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits
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DOI：
10.1049/iet-cds.2012.0361
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发表时间：
2013-09
期刊：
影响因子：
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通讯作者：
Xiaoming Chen;Hong Luo;Yu Wang;Yu Cao;Yuan Xie;Yuchun Ma;Huazhong Yang
中科院分区：
文献类型：
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作者：
Xiaoming Chen;Hong Luo;Yu Wang;Yu Cao;Yuan Xie;Yuchun Ma;Huazhong Yang
近年来，随机电报噪声(RTN)已成为纳米级电路中一个重要的可靠性问题。提出了一个16 nm工艺节点RTN影响下数字电路时间性能评估的仿真框架。提出了两种具有线性时间复杂度的快速算法：统计关键路径分析和基于正态分布的分析。仿真结果表明，RTN引起的电路时延退化和变异均为>；20%，最大退化和变异可达>；30%。文中还研究了电源调谐和栅极尺寸调整技术对抑制RTN的影响。
Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.