A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters
A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters
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DOI：
10.1109/asscc.2015.7387506
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发表时间：
2015-11
期刊：
影响因子：
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通讯作者：
Wei-Hsin Tseng;W. Lee;Chang-Yang Huang;Pao-Cheng Chiu
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文献类型：
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作者：
Wei-Hsin Tseng;W. Lee;Chang-Yang Huang;Pao-Cheng Chiu
提出了一种用于蜂窝应用的数字辅助无线发射系统的12位104 MS/s逐次逼近寄存器模数转换器（SARADC）。采用上电校准技术校正DAC电容失配并减小电容尺寸，从而降低输入缓冲器和基准电压源的电流消耗。总电容尺寸从12位匹配所需的3.6pF减小到0.6pF。ADC模拟核心面积为0.003mm2。经过校准后，在26 MHz采样率下的SFDR为88 dB，在104 MHz采样率下的SFDR为76.2dB。实测DNL和INL分别为0.5LSB和1. 1 LSB。该ADC通过结合多种技术实现高速和低功耗：数字校准、冗余、异步位循环、单调切换、25%占空比采样周期、3dB输入增益和全动态比较器1.2V/1.1V电源供电时，单个ADC内核的功耗为0.88 mW，整个I/Q ADC的功耗为6.1 mW，包括基准发生器和输入缓冲器。该ADC采用28 nm CMOS工艺制作。
A 12b 104MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration technique is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby relaxing the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6pF from 3.6pF required for 12-bit matching. The ADC analog core area is 0.003mm2. After calibration, this work achieves 88dB SFDR at 26MHz sampling rate and 76.2dB SFDR at 104MHz sampling rate. Measured DNL and INL are 0.5LSBs and 1. 1LSBs respectively. The ADC achieves both high speed and low power by combining several techniques: digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3dB input gain, and a fully dynamic comparator The power consumption from 1.2V/1.1V supplies is 0.88mW for a single ADC core and 6.1-mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28nm CMOS.