Formal design procedures for pass transistor switching circuits
Formal design procedures for pass transistor switching circuits
复制标题
传输晶体管开关电路的正式设计程序
DOI：
10.1109/jssc.1985.1052339
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发表时间：
1985
影响因子：
5.4
通讯作者：
G. Maki
中科院分区：
文献类型：
--
作者：
D. Radhakrishnan;S. Whitaker;G. Maki
提出了两种形式的设计技术来实现 NMOS 和 CMOS 技术中的传输逻辑网络。第一种技术使用改进的卡诺图最小化程序，它可以成为设计最多五个或六个变量的网络的有效工具。对于涉及六个以上变量的网络，通过修改传统的 Quine-McCluskey 方法来开发算法过程。硅面积的节省取决于晶体管数量以及互连结构。传输晶体管阵列的最大形貌规律性可以在控制变量集与空集中的传输变量集的交集中实现。这允许传递变量和控制变量彼此成直角流动。这一要求可能会增加设计中的晶体管数量，因此在拓扑规则性和晶体管数量之间需要进行权衡。对 CMOS 和 NMOS 绘制的单元进行了比较。
Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared.