A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
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具有高速晶圆级 IO 测试方案和考虑温度分布的自适应刷新的 1.2 V 20 nm 307 GB/s HBM DRAM
DOI：
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发表时间：
2017
影响因子：
5.4
通讯作者：
G. Jin
中科院分区：
文献类型：
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作者：
Kyomin Sohn;Won;Reum Oh;C. Oh;Seong;Min;Dong;Won;Sang;Je;Hye;Jae;Hyunui Lee;Seok;Y. Sohn;J. Choi;Yong;Seong;G. Jin
为满足高性能计算应用对高带宽的需求，设计了一种1.2V 20 nm 307 GB/s高带宽存储器（HBM）DRAM。HBM由缓冲芯片和多个核心芯片组成，每个核心芯片具有8 Gb DRAM单元阵列和额外的1 Gb ECC阵列。在高速晶圆级，U凸块IO测试方案和考虑温度分布的自适应刷新方案被提出，以保证测试覆盖率和稳定的工作在一个省电的方式。
A 1.2 V 20 nm 307 GB/s high-bandwidth memory (HBM) DRAM is presented to satisfy a high-bandwidth requirement of high-performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At-speed wafer level, a u-bump IO test scheme and an adaptive refresh scheme considering temperature distribution are proposed to guarantee test coverage and stable operation in a power-efficient manner.