Detailed routing violation prediction during placement using machine learning

Detailed routing violation prediction during placement using machine learning
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使用机器学习在贴装过程中进行详细的布线违规预测

DOI:
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发表时间:
2017
期刊:
International Symposium on VLSI Design, Automation and Test
影响因子:
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通讯作者:
L. Behjat
L. Behjat
中科院分区:
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文献类型:
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作者:
Aysa Fakheri Tabrizi;Nima Karimpour Darav;L. Rakai;A. Kennings;L. Behjat

文献摘要

被引文献

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22nm及以下设计规则的复杂性排除了将详细路由(DR)规则直接合并到放置算法中的可能性。然而,在放置过程中忽略路由可达性规则可能导致设计不可行。由全局路由器估计的拥塞通常用于放置期间的路由估计,但它不包括真正详细的路由违规,这对设计的可达性产生不利影响。目前,还没有一种方法能够直接预测详细的路由冲突。在本文中,我们提出了一种基于机器学习的方法来预测短路,这是详细路由违规的主要组成部分。所提出的方法可以集成到放置工具中,并在放置过程中作为指导,以减少在详细布线阶段发生的短路次数。实证结果表明,该方法对无空头违规区域的空头预测成功率为88%,错误预测率仅为16%。
The complexity of design rules at 22nm and below precludes direct incorporation of detailed routing (DR) rules into a placement algorithm. However, ignoring routability rules during the placement process may result in infeasible designs. The congestion estimated by a global router is conventionally used for routing estimation during placement, but it does not include real detailed routing violations, which adversely affect the routability of a design. Presently, there are no methods that directly aim to predict detailed routing violations. In this paper we propose a machine learning based method to predict the shorts that are a major component of detailed routing violations. The proposed method can be integrated into a placement tool and be used as a guide during the placement process to reduce the number of shorts happening in the detailed routing stage. Empirical results show that our method is successful in predicting 88% of the shorts with only 16% incorrectly predicting shorts in no short violation area.