Towards Massive MIMO Channel Emulation: Channel Accuracy Versus Implementation Resources
Towards Massive MIMO Channel Emulation: Channel Accuracy Versus Implementation Resources
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DOI：
10.1109/tvt.2020.2980583
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发表时间：
2020-03
影响因子：
6.8
通讯作者：
Pengda Huang;M. Tonnemacher;Yongjiu Du;D. Rajan;J. Camp
中科院分区：
文献类型：
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作者：
Pengda Huang;M. Tonnemacher;Yongjiu Du;D. Rajan;J. Camp
信道仿真广泛用于控制无线信道和重放场景，以进行可重复的实验和评估。描述大规模多输入多输出（MIMO）系统的传播特性是一项挑战，因为创建代表性场景所需的信道数量快速缩放，以及准确建模信道矩阵中存在的复杂相互依赖性。尽管如此，仿真大规模MIMO信道的能力对于下一代蜂窝协议和算法的开发和测试至关重要。为了实现大规模MIMO信道仿真解决方案的规模，在本文中，我们研究了信道仿真保真度与使用分析建模和基于FPGA的实现所消耗的硬件资源之间的权衡。为了减少我们的设计的内存占用，我们优化我们的信道仿真使用迭代结构生成基于几何的通道规模。此外，不同的通道更新速率和字长选择的影响进行了评估，可以显着提高FPGA上的实现效率。
Channel emulation is widely used to control wireless channels and replay scenarios for repeatable experimentation and evaluation. Characterizing the propagation of massive Multiple-Input Multiple-Output (MIMO) systems, is challenging due to the rapid scaling of the number of channels needed to create representative scenarios as well as accurately modeling complex interdepedencies that exist within the channel matrix. Nonetheless, having the ability to emulate massive MIMO channels is critical for the development and testing of next-generation cellular protocols and algorithms. To achieve such scale for massive MIMO channel emulation solutions, in this paper, we study the tradeoff in channel emulation fidelity versus the hardware resources consumed using both analytical modeling and FPGA-based implementations. To reduce the memory footprint of our design, we optimize our channel emulation using an iterative structure to generate geometry-based channels at scale. In addition, the effects of varying the channel update rate and word length selection are evaluated in the paper and can significantly improve the implementation efficiency on an FPGA.