Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links
Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links
复制标题
使用无线链路对片上网络进行高效的硅后验证
DOI：
--
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Sujay Deb
中科院分区：
文献类型：
--
作者：
Sidhartha Sankar Rout;K. Basu;Sujay Deb
现代复杂的互连系统增强了新的功能，以服务于越来越多的片上处理元件（PE）。在当代设计中实现所需的性能、功率和可靠性；芯片网络（NoC）通过额外的硬件和管道阶段得到加强。在基线有线NoC的基础上补充了无线集线器，以实现高效的芯片内长距离通信。随着网络的日益复杂，在预硅验证阶段，保证互连模块的功能正确性是极其困难的。因此，必须为noc设计一个强大的后硅验证机制，以保证系统的无错误功能。本文利用无线NoC （WNoC）中无线集线器的功能，建立了一种新的通信网络后硅验证模型。该方法在不增加跟踪缓冲区大小和跟踪带宽要求方面的额外开销的情况下，可以更好地观察系统在路由错误和丢包等瞬态数据包故障情况下的可观察性。与使用该无线方案的有线网络相比，在故障检测和路径重建方面总体提高了30%。无线收发器建设性地利用现有的网络将走线传输到外部调试分析仪，从而在提高走线通信速度的同时不需要额外的走线总线。
Modern complex interconnect systems are augmented with new features to serve the increasing number of on-chip processing elements (PE). To achieve the desired performance, power and reliability in the contemporary designs; Network-on-Chips (NoC) are reinforced with additional hardware and pipeline stages. Wireless hubs are supplemented on top of the baseline wired NoC for efficient intra-chip long distance communications. With the increasing complexity of the network, it is extremely difficult to ensure the functional correctness of the interconnect module at the pre-silicon verification stage. Hence, a robust post-silicon validation mechanism for NoCs has to be devised to guarantee the error-free functioning of the system. This paper exploits the capabilities of the wireless hubs present in wireless NoC (WNoC) to establish a novel post-silicon validation model for communication networks. The proposed method facilitates a better observability of the system in case of transient packet faults like misroute and packet-drop without any additional overhead in term of trace buffer size and trace bandwidth requirement. An overall 30% improvement in fault detection and path reconstruction is observed in comparison to the wired network using this wireless scheme. The wireless transceivers constructively use the existing network to transport the traces till the external debug analyzer, thus eliminating the need of additional trace bus while elevating the speed of trace communication.