A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications
A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications
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DOI：
10.1109/mwscas48704.2020.9184526
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发表时间：
2020-08
期刊：
影响因子：
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通讯作者：
N. Tasneem;I. Mahbub
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文献类型：
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作者：
N. Tasneem;I. Mahbub
本文提出了一种完全可重构的读出电路，包括一个斩波稳定的神经放大器和一个连续逼近寄存器（SAR）模数转换器（ADC），用于神经信号记录应用。由于目标神经信号-动作电位（ap）和局部场电位（LFPs）在峰值幅度上不同，并且占用不同的频率带宽，因此增益和带宽可重构性将有利于提高功率和噪声性能。读出电路采用180nm标准CMOS技术设计。在0.1 Hz ~ 250hz频段检测lfp，实现了50.3 dB的中频增益；在267 Hz ~ 20.8 kHz频段检测ap，实现了63.4 dB的中频增益。LFP和AP配置的神经放大器的总功耗分别为1.54µW和1.94µW。输入参考噪声分别为0.97µVrms （0.1 Hz - 250 Hz）和0.44µVrms (250 Hz - 5 kHz)，两种配置的噪声效率因子（NEF）分别为1.27和1.21。它通过实现直流伺服回路（DSL），在电极-组织界面处抑制产生的高达40 mV的大直流偏置。与DSL的偏置电压为0.23 mV，可用于神经网络实验。启用阻抗升压回路，发现直流输入阻抗在1.77 - 2.27 GΩ范围内，引入阻抗可重构性以与电极阻抗匹配。SAR-ADC具有10 - 40 ksamples/s的可变采样频率，演示了ap和lfp的数字化，分辨率从8 - 10位。整个AFE具有良好的兼容性，可以记录神经信号，同时将大直流偏置降低到0.23 mV。
This paper presents a fully reconfigurable readout circuit including a chopper-stabilized neural amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC) for neural signal recording applications. Since the target neural signals - action potentials (APs) and local field potentials (LFPs) differ in the peak amplitude while occupying different frequency bandwidths, gain, and bandwidth reconfigurability would be advantageous in improving power and noise performance. The readout circuit is designed in 180 nm standard CMOS technology. It achieves the mid-band gain of 50.3 dB in the frequency band of 0.1 Hz - 250 Hz to detect the LFPs, and 63.4 dB in 267 Hz - 20.8 kHz for detecting the APs. The neural amplifier consumes a total power of 1.54 µW and 1.94 µW for LFP and AP configurations, respectively. The input-referred noises have been achieved as 0.97 µVrms (0.1 Hz - 250 Hz), and 0.44 µVrms (250 Hz - 5 kHz), leading to a noise efficiency factor (NEF) of 1.27 and 1.21, for the two configurations, respectively. It rejects the generated large DC offset up to 40 mV at the electrode-tissue interface, by implementing a DC servo loop (DSL). The offset voltage with the DSL becomes 0.23 mV, which is acceptable for the neural experiments. Enabling the impedance boosting loop, the DC input impedance is found to be within the range of 1.77 - 2.27 GΩ, introducing the reconfigurability in impedance for matching with the electrode impedance. The SAR-ADC having a varying sampling frequency ranging from 10 - 40 ksamples/s demonstrates to digitize the APs and the LFPs with the resolution from 8 - 10 bits. The entire AFE provides good compatibility to record the neural signal while lowering the large DC offset down to 0.23 mV.