Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction
Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction
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DOI：
10.1109/tc.2016.2621758
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发表时间：
2017-05
影响因子：
3.7
通讯作者：
Hao Wang;Kai Zhao;Minjie Lv;Xuebin Zhang;Hongbin Sun;Tong Zhang
中科院分区：
文献类型：
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作者：
Hao Wang;Kai Zhao;Minjie Lv;Xuebin Zhang;Hongbin Sun;Tong Zhang
虽然新兴的3D DRAM产品可以显著提高计算系统的性能，但相对较高的成本是阻碍其在现实生活中广泛采用的最关键问题之一。直观地说，可以利用强大的存储器容错能力来降低DRAM芯片的制造成本，如果制造成本的节省可以抵消存储器容错的成本开销，那么总成本就会降低。然而，这种简单的概念只适用于3D DRAM，因为：(1)堆叠式逻辑芯片可以在3D DRAM芯片内唯一实现存储器容错，避免了对主机CPU和CPU-DRAM接口的任何更改。(2)随着3D DRAM芯片内部逻辑芯片和DRAM芯片的全部所有权，DRAM制造商可以充分挖掘潜力，真正将3D DRAM位成本降至最低。根据这一直觉，我们开发了一种3D DRAM容错设计策略。它可以以非常小的冗余和延迟开销实现对弱DRAM单元的非常强的容忍性。关键是要结合利用弱信元的可检测性和纠错码(ECC)解码的运行时可配置性。此外，该设计策略可以优雅地接受弱小区检测的不准确性(例如，弱小区漏检测和误检测)。我们进行了深入的数学分析，结果表明，在冗余开销为1：8(与目前的ECC DIMM相同)的情况下，该设计策略在100%和90%的弱单元已知的情况下，可以容忍高达$10^-4}$和6$\x 10^-5}$的弱单元速率。使用Micron的混合存储立方体(HMC)3D DRAM芯片作为测试载体，对其实现成本进行了评估，结果表明该芯片的逻辑芯片仅消耗不到0.4mm2(45 nm节点)。使用CPU和DRAM模拟器，我们进一步对各种计算基准进行了模拟，结果表明，该设计方案平均只引起不到2%的性能下降。
Although the emerging 3D DRAM products can significantly improve the computing system performance, the relatively high cost is one of the most critical issues that prevent their wide real-life adoption. Intuitively, a strong memory fault tolerance can be leveraged to reduce the fabrication cost of DRAM dies, and the total cost will reduce if the fabrication cost saving can off-set the cost overhead of memory fault tolerance. Nevertheless, such a simple concept can be a practically viable option only for 3D DRAM because: (1) The stacked logic die can solely implement memory fault tolerance inside 3D DRAM chips, obviating any changes on the host CPUs and CPU-DRAM interfaces. (2) With the total ownership of both the logic die and DRAM dies inside 3D DRAM chips, DRAM manufacturers can fully exploit the potential to truly minimize the 3D DRAM bit cost. Following this intuition, we developed a 3D DRAM fault tolerance design strategy. It can achieve a very strong tolerance to weak DRAM cells at very small redundancy and latency overhead. The key is to cohesively leverage the detectability of weak cells and runtime configurability of error correction code (ECC) decoding. In addition, this design strategy can gracefully embrace the inaccuracy of weak cell detection (e.g., weak cell miss-detection and false-detection). We carried out thorough mathematical analysis, and the results show that, under the redundancy overhead of 1:8 (same as today’s ECC DIMM), this design strategy can tolerate the weak cell rate of as high as $10^{-4}$ and 6 $\times 10^{-5}$ if 100 and 90 percent of all the weak cells are known in prior. Using Micron’s hybrid memory cube (HMC) 3D DRAM chips as the test vehicle, we evaluated the implementation cost and the results show that it only consumes less than 0.4 mm2 (45 nm node) on the logic die. Using CPU and DRAM simulators, we further carried out simulations over a variety of computing benchmarks and the results show that this design solution only incurs less than 2 percent performance degradation on average.