A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines
A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines
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DOI：
10.1109/icecs.2018.8617948
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发表时间：
2018-12
期刊：
影响因子：
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通讯作者：
Nico Angeli;K. Hofmann
中科院分区：
文献类型：
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作者：
Nico Angeli;K. Hofmann
提出了一种新型数控并联电容逆变器延迟元件及其设计过程。数字并联电容器由二进制传输门组成，与使用单独 MOSFET 用于开关和电容器的最先进解决方案相比，总电容和分辨率要小得多。这样可以降低功耗并缩小面积，使并联电容器逆变器成为 GHz 范围内高分辨率延迟线的有效解决方案。 MSB 和 LSB 并联电容器的不同拓扑通过降低 CMOS 反相器的最小电容负载进一步提高了效率。所提出的延迟元件在 65 nm CMOS 工艺中进行了验证，在 2.5 GHz 全数字多相延迟锁定环中实现了步长为 0.82 ps 的四级延迟线。
A new digitally controlled shunt-capacitor inverter delay element and its design procedure are presented. The digital shunt-capacitors consist of binary scaled transmission gates and have a much smaller total capacitance and resolution than state-of-the-art solutions using separate MOSFETs for switches and capacitors. This results in a lower power consumption and smaller area making the shunt-capacitor inverter an efficient solution for high-resolution delay lines in the GHz range. Different topologies for the MSB and LSB shunt-capacitors further improve the efficiency by reducing the minimum capacitive loading of the CMOS inverter. The proposed delay element is verified in a 65 nm CMOS process implementing a four stage delay-line with a step size of 0.82 ps in a 2.5 GHz all-digital multiphase delay locked loop.