High performance Viterbi decoder design
High performance Viterbi decoder design
复制标题
高性能维特比译码器设计
DOI：
10.1007/s10586-018-2295-8
复制
发表时间：
2019
期刊：
影响因子：
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通讯作者：
S. Mohanraj
中科院分区：
文献类型：
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作者：
V. Kavitha;S. Mohanraj
维特比解码器可能是一个正则模块，在对应的框架中，能量也解码不需要辅助需求。注册交换（RE）结构设计最需要减少解密不活动，但由于其二次力的利用，不适合通信框架。本文介绍了另一种SMU结构工程，它结合了前向追溯和后向追溯的思想。那些破译不活动的建议SMU计算可能是主要的L+M。此外，我们还展示了基于推荐的SMU算法的强制生产建筑设计。推荐的结构工程在Xilinx ISE 12中执行。3的焦点器件可能是Vertex6 FPGA。建议构造模型的控制利用率略高于那些三分球。
Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization. In this paper, it is recommended another SMU structural engineering which combines the idea of the trace-forward and also trace-back. Those deciphering inactivity of the suggested SMU calculation may be main L+M. Besides, we display a force productive building design for the recommended SMU algorithm. The recommended structural engineering is executed in Xilinx ISE 12. 3 for focus gadget may be Vertex6 FPGA. The control utilization of the suggested construction modeling is marginally higher over those 3-pointer.