Expected Failures in 3-D Technology and Related Failure Analysis Challenges
Expected Failures in 3-D Technology and Related Failure Analysis Challenges
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DOI：
10.1109/tcpmt.2018.2810321
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发表时间：
2018-04
期刊：
影响因子：
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通讯作者：
I. De Wolf;K. Croes;E. Beyne
中科院分区：
文献类型：
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作者：
I. De Wolf;K. Croes;E. Beyne
在介绍了3d技术之后，通过硅通孔（TSV）和堆叠选项，本文概述了3d技术中可能出现的故障，并列出了可用于发现这些故障和相关挑战的潜在故障分析（FA）技术。讨论了tsv中可能出现的各种失效机制和影响，如Cu泵送、空洞、衬管/势垒击穿、电迁移、机械应力冲击、Cu扩散、等离子体诱导损伤和隔离区。此外，由于背面加工（薄化引起的损坏、充电和Cu暴露）和堆叠（错位、空洞、焊料挤压、静电放电、应力引起的开裂和分层）而导致的故障也被列出。强调了机械应力和芯片封装相互作用作为三维技术失效的主要威胁的重要性。本文没有详细讨论FA技术（提供了参考资料）。显然，需要能够检测故障的技术，例如小（微米和亚微米范围）裂纹、空洞和分层区域（平面和垂直）。
After an introduction to 3-D technology, and through silicon via (TSV)- and stacking options, this paper provides an overview of failures that can be expected in 3-D technology and lists the potential failure analysis (FA) techniques that can be applied to find these failures and the related challenges. Various failure mechanisms and effects that can be expected in TSVs, such as Cu pumping, voids, liner/barrier breakdown, electromigration, mechanical stress impact, Cu diffusion, plasma-induced damage, and the keep-out-zone, are discussed. Also, failures due to backside processing (thinning-induced damage, charging, and Cu exposure) and stacking (misalignment, voids, solder squeeze-out, electrostatic discharge, stress-induced cracking, and delamination) are listed. The importance of mechanical stress and chip–package interaction as a main threat for failures in 3-D technology is highlighted. The FA techniques are not discussed in detail (references are provided). There is a clear need for techniques that can detect failures, such as small (micrometer and submicrometer range) cracks, voids, and delaminated regions (both planar and vertical).