Selective Area Growth: A Promising Way for Recessed Gate GaN MOSFET With High Quality MOS Interface
Selective Area Growth: A Promising Way for Recessed Gate GaN MOSFET With High Quality MOS Interface
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DOI：
10.1109/led.2016.2590821
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发表时间：
2016-07
影响因子：
4.9
通讯作者：
Y. Zheng;F. Yang;L. He;Y. Yao;Z. Shen;G. Zhou;Z. He;Y. Ni;D. Zhou;J. Zhong;X. Zhang-;Z. Wu;B. Zhang;Y. Liu
中科院分区：
文献类型：
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作者：
Y. Zheng;F. Yang;L. He;Y. Yao;Z. Shen;G. Zhou;Z. He;Y. Ni;D. Zhou;J. Zhong;X. Zhang-;Z. Wu;B. Zhang;Y. Liu
基于选择性区域生长（SAG）技术，成功制备了增强型GaN凹进式栅极MOSFET，其栅极俘获效应可忽略不计，在栅极偏压摆幅高达10 V时，呈现出极小的50 mV阈值电压（Vth）迟滞。与干法刻蚀制造的凹进式栅极GaN MOSFET的较大Vth迟滞相比，Vth迟滞与等离子体引起的晶格损伤相关陷阱之间的相关性干法刻蚀工艺已得到证实。此外，由于 MOS 沟道迁移率较高，SAG 凹进 MOSFET 显示出较低的导通电阻。我们相信，SAG MOSFET 的所有这些卓越性能都归功于 Al2O3/GaN MOS 界面处的无损伤高质量 GaN 表面，这表明 SAG 是一种有前途的替代技术，可用于功率开关应用的稳定 GaN MOSFET。
Based on the selective area growth (SAG) technique, an enhancement mode GaN recessed gate MOSFET was fabricated successfully with negligible gate trapping effect, presenting an extremely small threshold voltage (Vth) hysteresis of 50 mV at a gate bias swing up to 10 V. Compared with the larger Vth hysteresis of a recessed gate GaN MOSFET fabricated by dry-etching, the correlation between the Vth hysteresis and the lattice damage related traps caused by plasma dry etching process has been confirmed. Furthermore, the SAG recessed MOSFET shows a lower turn-ON resistance due to the higher MOS channel mobility. We believe that all of these superior performance of SAG MOSFET are attributed to the damage free high quality GaN surface at the Al2O3/GaN MOS interface, which indicates that the SAG is a promising alternative technique toward stable GaN MOSFET for the power switching applications.