An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network
An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network
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DOI：
10.1109/ssci.2016.7850175
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发表时间：
2016-09
期刊：
影响因子：
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通讯作者：
Anju P. Johnson;D. Halliday;Alan G. Millard;A. Tyrrell;J. Timmis;Junxiu Liu;J. Harkin;L. McDaid;Shvan Karim
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文献类型：
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作者：
Anju P. Johnson;D. Halliday;Alan G. Millard;A. Tyrrell;J. Timmis;Junxiu Liu;J. Harkin;L. McDaid;Shvan Karim
人类的大脑具有自我修复的能力。大脑的这种可塑性促使研究人员开发出具有类似容错和自我修复能力的系统。近年来的研究表明，星形胶质细胞和神经元之间的相互作用可以驱动星形胶质细胞-神经元双向耦合系统的类脑自我修复。本文介绍了一种基于FPGA的仿生自修复结构的硬件实现。我们还介绍了基于fpga的硬件高效容错系统的简化架构。这是基于星形细胞-神经元网络逆行信号的原理，通过简化星形细胞内的钙动力学。硬件优化实现显示硬件利用率降低90%以上，证明了大规模星形细胞-神经元网络的有效实现。在100%局部故障的情况下，两种星形胶质细胞模型的平均峰值率为0:027。
The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.