Oscillator without a combinatorial loop and its threat to FPGA in data centre
Oscillator without a combinatorial loop and its threat to FPGA in data centre
复制标题
无组合环的振荡器及其对数据中心FPGA的威胁
作者：
Takeshi Sugawara;Kazuo Sakiyama;S. Nashimoto;Suzuki Daisuke;T. Nagatsuka
虚拟现场可编程的门阵列（FPGA）是一种新兴技术，可将多个用户放在具有逻辑隔离的同一FPGA面料中。安全研究人员通过利用FPGA的模拟本质研究了虚拟FPGA中的新威胁，并提出了对逻辑隔离的拟议攻击。这些攻击使用包括组合循环的振荡器仅使用数字组件访问模拟域。有趣的是，该领域的系统禁止通过设计规则检查组合循环。在这封信中，作者研究如果禁止组合循环，则足以阻止常规攻击。他们通过在没有组合循环的情况下显示振荡器来负面回答这个问题。他们还展示了如何通过设计规则检查检测和拒绝提出的振荡器。
Virtual field-programmable gate array (FPGA) is an emerging technology to put multiple users in the same FPGA fabric with logical isolation. Security researchers have studied new threats in virtual FPGA and proposed attacks on the logical isolation by exploiting analogue natures of FPGA. These attacks use an oscillator comprising a combinatorial loop to have access to the analogue domain using digital components only. Interestingly, the system in the field prohibits a combinatorial loop by a design rule check. In this Letter, the authors study if prohibiting a combinatorial loop is sufficient to thwart the conventional attacks. They negatively answer the question by showing oscillators without a combinatorial loop. They also show how to detect and reject the proposed oscillators by a design rule check.