Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling
Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling
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DOI：
10.1109/cicc.2006.321010
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发表时间：
2006-09
期刊：
影响因子：
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通讯作者：
E. Ibe;S. Chung;S. Wen;H. Yamaguchi;Y. Yahagi;H. Kameyama;Shigehisa Yamamoto;T. Akioka
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文献类型：
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作者：
E. Ibe;S. Chung;S. Wen;H. Yamaguchi;Y. Yahagi;H. Kameyama;Shigehisa Yamamoto;T. Akioka
综述了CMOS SRAM多单元翻转（MCU）的最新研究进展，并讨论了缩放效应。发展了空间和时间域自动分类技术，并应用于130 nm SRAM在TSL和CYRIC准单能中子辐照下的单粒子翻转。测试表明MCU功能对数据模式的依赖性非常高，通常是“全”0“/”1“和棋盘。三个错误传播类别与41模式固有的设备架构被确定。新的MCU功能，其中错误可以通过重写，但Idd逐步增加取决于MCU的多重性，被确定。对于“全0/1”模式，发现双比特错误的比率甚至高于单比特错误的比率。双位错误的大部分位于沿着字线（WL）的最近邻域（NN）位置中。强调的基本机制可以是电荷收集-扩散或寄生双极动作。但大多数特性只能通过作者提出的一种新的MCU机制MCBI（多耦合双极相互作用）来充分阐明，为SEU容忍亚100 nm设计提供线索
Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data patterns, typically "All `0'/`1'" and checkerboard. Three error propagation categories with 41 modes inherent in device architectures are identified. Novel MCU features, in which errors can be corrected by rewriting but Idd increases stepwise depending on MCU multiplicity, are identified. With "All `0'/`1'" pattern, ratio of double bit error is found to be even higher than that of single bit errors. The majority of the double bit error is in nearest neighborhood (NN) position along word line (WL). Underlining basic mechanism can be either charge collection-diffusion or parasitic bipolar actions. But most features can be elucidated only fully by a novel MCU mechanism MCBI (multi-coupled bipolar interaction) proposed by the authors, giving clues for SEU tolerant sub-100nm design