CHARACTERIZATION AND MODELING OF MISMATCH IN MOS-TRANSISTORS FOR PRECISION ANALOG DESIGN
CHARACTERIZATION AND MODELING OF MISMATCH IN MOS-TRANSISTORS FOR PRECISION ANALOG DESIGN
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DOI：
10.1109/jssc.1986.1052648
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发表时间：
1986-12-01
影响因子：
5.4
通讯作者：
COPELAND, MA
中科院分区：
文献类型：
--
作者：
LAKSHMIKUMAR, KR;HADAWAY, RA;COPELAND, MA
一种表征方法，准确地预测漏极电流在一个很宽的工作范围内使用最小的测量数据集的失配。失配的物理原因进行了详细讨论，为p和n沟道器件。统计方法用于开发分析模型，该模型将失配与器件尺寸相关联。结果表明，这些模型是有效的小几何形状的设备。广泛的实验数据从3-/spl μ/m CMOS工艺被用来验证模型。讨论了晶体管匹配研究在高性能数模转换器（DAC）设计中的应用。提出了一种电路设计方法，突出了电路成品率和器件匹配精度之间的密切相互作用。由于晶体管匹配行为的知识和系统设计方法，已经可以实现大于97%的电路成品率。
A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.