Automatic generation of microarchitecture simulators
Automatic generation of microarchitecture simulators
复制标题
自动生成微架构模拟器
DOI：
10.1109/iccl.1998.674159
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发表时间：
1998
期刊：
影响因子：
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通讯作者：
Rajiv Gupta
中科院分区：
文献类型：
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作者：
Soner Önder;Rajiv Gupta
我们描述了 UPFAST 系统，该系统根据使用称为架构描述语言（ADL）的特定领域语言编写的微架构规范自动生成周期级模拟器、汇编器和反汇编器。使用 UPFAST 系统，可以轻松地将现有架构的模拟器重新定位为修改后的架构，因为只需修改输入规范即可自动生成新的模拟器。 UPFAST 还允许以最小的努力将模拟器移植到不同的平台。我们已经能够在短短三个月内开发出三种模拟器，从简单的流水线处理器到复杂的乱序问题处理器。虽然架构的规格从 5000 到 6000 行 ADL 代码不等，但自动生成的软件的大小从 20000 到 300000 行 C++ 代码不等。对于类似架构，自动生成的模拟器比手动编码的模拟器慢不到 2 倍。
We describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitecture specification written in a domain specific language called the Architecture Description Language (ADL). Using the UPFAST system, it is easy to retarget a simulator for an existing architecture to a modified architecture since one has to simply modify the input specification and the new simulator is generated automatically. UPFAST also allows porting of simulators to different platforms with minimal effort. We have been able to develop three simulators ranging from simple pipelined processors to complicated out-of-order issue processors over a short period of three months. While the specifications of the architectures varied from 5000 to 6000 lines of ADL code, the sizes of automatically generated software varied from 20000 to 300000 lines of C++ code. The automatically generated simulators are less than 2 times slower than hand coded simulators for similar architectures.