Electrical characterization and impact on signal integrity of new basic interconnection elements inside 3D integrated circuits
Electrical characterization and impact on signal integrity of new basic interconnection elements inside 3D integrated circuits
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3D 集成电路内部新型基本互连元件的电气特性及其对信号完整性的影响
DOI：
10.1109/ectc.2011.5898659
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
B. Fléchet
中科院分区：
文献类型：
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作者：
J. Roullard;S. Capraro;Alexis Farcy;Thierry Lacrevaz;C. Bermond;Patrick Leduc;J. Charbonnier;C. Ferrandon;C. Fuchs;B. Fléchet
3D集成技术的发展揭示了几种基本的互连元素，如通过硅孔、再分布层、铜柱和凸起，以在3D电路中传输信号。在全球三维互连链中，互连元件对高速信号完整性的影响需要研究。首先对每个元件进行连续表征，并从测量或仿真中提取等效的频域电模型。接下来，将这些模型真实地链接起来，模拟全球3D- ic互连链的信号完整性性能（随延迟下降），以便在3D集成中涉及的众多选项中确定最佳策略。三项研究详细调查了路由策略，芯片堆栈方向的选择（面对面或面对面），以及各种可用3D技术的比较，从而为未来的3D产品提供全球建议。
Developments in 3D integration technology reveal several basic interconnect elements, as Through Silicon Via, Redistribution Layers, Cu-Pillar and bumps to transmit signals inside 3D circuits. Impact of the interconnect elements on high speed signal integrity all along the global 3D interconnection chain requires investigation. First each element was successively characterized and an equivalent electrical model was extracted in the frequency domain from measurements or simulations. Next these models were realistically chained to simulate the signal integrity performance, declined as delay, of the global 3D-IC interconnection chain in order to determine the best strategies among the multitude of options involved in 3D integration. Three studies were investigated in detail regarding routing strategy, the choice of chip stack orientations (Face-to-Face or Face-to-Back), and the comparison of various 3D technologies available, resulting in global recommendations for future 3D products.