Security-aware SoC test access mechanisms
Security-aware SoC test access mechanisms
复制标题
安全感知 SoC 测试访问机制
DOI：
10.1109/vts.2011.5783765
复制
发表时间：
2011
期刊：
影响因子：
--
通讯作者：
R. Karri
中科院分区：
文献类型：
--
作者：
Kurt Rosenfeld;R. Karri
测试访问机制是数字系统中的关键组成部分。它们不仅影响生产和运营经济，而且影响系统安全。我们提出了一个安全增强系统级芯片（SoC）测试访问，解决了不可信的核心所带来的威胁。该方案保持了共享布线（总线或菊花链）的经济性，同时实现了星型拓扑测试访问布线的大部分安全优势。使用所提出的方案，测试器能够与每个核建立不同的加密会话密钥，从而显著减少在一个或多个核包含恶意或不可信逻辑的情况下的暴露。所提出的方案不在功能路径之外，并且不影响功能时序或功耗。
Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic. The proposed scheme is out of the functional path and does not affect functional timing or power consumption.