A real-time architecture for reference frame compression for high definition video coders

A real-time architecture for reference frame compression for high definition video coders
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DOI:
10.1109/iscas.2015.7168765
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发表时间:
2015-05
期刊:
2015 IEEE International Symposium on Circuits and Systems (ISCAS)
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通讯作者:
D. Silveira;Guilherme Povala;Lívia Amaral;B. Zatt;L. Agostini;M. Porto
D. Silveira;Guilherme Povala;Lívia Amaral;B. Zatt;L. Agostini;M. Porto
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其他
文献类型:
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作者:
D. Silveira;Guilherme Povala;Lívia Amaral;B. Zatt;L. Agostini;M. Porto

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当前操作数字视频的电池供电设备必须将此过程的能耗视为一个重要问题,特别是在处理高清或超高清视频时。在这种情况下,本文提出了一种解决方案,以减少在运动估计过程中的外部存储器通信,以减少在视频编码系统中的能量消耗。在本文中提出的方案被称为差分参考帧编码器,它实现了一种算法,结合两种技术,以减少内存带宽:差分编码的基础上,简化帧内预测过程,以减少重构样本的空间冗余,和半固定长度编码应用于差分编码步骤产生的残差。该解决方案达到了一个平均无损压缩比高于57%的评估高清1080p视频序列,同时支持随机访问参考帧块。提出的硬件架构(编码器和解码器),描述了在VHDL和合成目标ASIC为65 nm和180 nm的台积电标准单元库。实验结果表明,在65nm下,该结构能够以30 fps的速度处理UHD 2160p(3840×2160个样本)或120 fps的速度处理HD 1080p(1920×1080个样本),功耗为0.885mW。
Current battery-powered devices that manipulate digital videos must consider the energy consumption of this process as an important issue, especially when high or ultra-high definition videos are handled. In this scenario, this paper proposes a solution to reduce the energy consumption in video coding systems by reducing the external memory communication during the motion estimation. The scheme presented in this paper is called Differential Reference Frame Coder and it implements an algorithm that combines two techniques to reduce the memory bandwidth: a differential coding based on a simplified intra-prediction process, to reduce the spatial redundancy of the reconstructed samples, and a semi-fixed length coding applied in the residues generated by the differential coding step. This solution reaches an average lossless compression ratio higher than 57% for the evaluated HD 1080p video sequences whereas supporting random access to reference frame blocks. The proposed hardware architectures (Coder and Decoder) were described in VHDL and synthesized targeting ASIC for 65nm and 180nm TSMC standard-cell libraries. The results show that with 65nm, the architectures are able to process UHD 2160p (3840×2160 samples) at 30 fps or HD 1080p (1920×1080 samples) at 120 fps with a power dissipation of 0.885mW.