NEM Relay-Based Sequential Logic Circuits for Low-Power Design
NEM Relay-Based Sequential Logic Circuits for Low-Power Design
复制标题
用于低功耗设计的基于 NEM 继电器的时序逻辑电路
DOI：
--
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发表时间：
2013
影响因子：
2.4
通讯作者：
P. Balsara
中科院分区：
文献类型：
--
作者：
R. Venkatasubramanian;S. Manohar;P. Balsara
纳机电（NEM）继电器是一类很有前途的新兴器件，它提供零关态泄漏，表现得像一个理想的开关。零泄漏操作已经在使用这些继电器的低功耗逻辑设计中产生了很多兴趣。<citerefgrp><citeref refid="ref2"></citeref></citerefgrp>本文介绍了各种时序电路拓扑结构，使用NEM继电器，并分析其功耗，性能和面积的权衡。机械延迟与栅极-基极电压<formula formulatype="inline"><tex Notation="TeX">$V_{gb}$</tex></formula>成反比。本文还提出了一种基于集成倍压电路的触发器，使性能提高了2 <formula formulatype="inline"><tex Notation="TeX">$ 通过</tex></formula>过驱动<formula formulatype="inline"><tex Notation="TeX">$V_{gb}$来增加$倍</tex></formula>。一个机电模型，占机械，电气和分散效应的悬浮门继电器工作在1 V的标称空气间隙为5-10 nm已开发的基础上发表的制造结果。<citerefgrp><citeref refid="ref1"/></citerefgrp>利用NEM继电器设计了三个时序逻辑基准电路，验证了所提出电路工作的正确性。本研究探讨不同的继电器为基础的锁存器和触发器的拓扑结构，提出了快速时序电路，可以工作在<formula formulatype="inline"><tex Notation="TeX">1/2 t_{m}$</tex></formula>的频率（理论上最快的频率为NEM继电器逻辑电路），并进一步提高速度的时序电路的分布式充电升压。
Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays <citerefgrp><citeref refid="ref1"/></citerefgrp>, <citerefgrp><citeref refid="ref2"> </citeref></citerefgrp>. This paper presents various sequential circuit topologies using NEM relays and analyzes their power, performance, and area tradeoffs. The mechanical delay is inversely proportional to the gate-base voltage <formula formulatype="inline"><tex Notation="TeX">$V_{gb}$</tex></formula>. This paper also presents an integrated voltage doubler-based flip-flop that improves the performance by 2<formula formulatype="inline"><tex Notation="TeX">$ imes$</tex></formula> by overdriving <formula formulatype="inline"><tex Notation="TeX">$V_{gb}$</tex></formula>. An electromechanical model which accounts for the mechanical, electrical, and dispersion effects of the suspended gate relay operating at 1 V with a nominal air gap of 5–10 nm has been developed based on published fabrication results in <citerefgrp> <citeref refid="ref1"/></citerefgrp>. Three sequential logic benchmark circuits were designed using NEM relays to verify the correctness of operation of the proposed circuits. This study explores different relay-based latch and flip-flop topologies, proposes fast sequential circuits that can operate at a frequency of <formula formulatype="inline"><tex Notation="TeX">$1/2t_{m}$</tex></formula> (theoretical fastest frequency for NEM relay logic circuits) and further improves speed of sequential circuits by distributed charge boosting.