Arria™ 10 device architecture
Arria™ 10 device architecture
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Arria™ 10 器件架构
DOI：
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发表时间：
2015
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通讯作者：
B. Ang
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文献类型：
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作者：
Jeffrey Tyhach;M. Hutton;Sean Atsatt;Arifur Rahman;B. Vest;D. Lewis;M. Langhammer;Sergey Y. Shumarayev;T. Hoang;Allen Chan;D. Choi;D. Oh;Hae;Jack Chui;Ket Chiew Sia;Edwin Kok;Wei;B. Ang
本文介绍了Arria 10，一个高密度的FPGA系列的架构上的台积电20 SOC工艺。该器件的设计包括一个嵌入式双核1.5 GHz ARM A9子系统，带外设，超过1 M逻辑元件（LE）和1.7M用户触发器，以及组织成可配置存储器块的64 Mb嵌入式存储器。Arria 10系列也是第一个包含强化单精度IEEE 754浮点的主流FPGA系列，总吞吐量为1.3 TFLOP。设备I/O由28 G可编程收发器组成，具有增强的PMA架构、加固的PCIe子块和加固的DDR外部存储器控制器。数字辅助模拟校准的新方法用于解决工艺变化。该结构针对28 nm FPGA进行了优化，以大幅减小芯片尺寸并提高功耗，并包括用于微重定时的时间借用FF、用于提高可布线性的三态长线、LAB群集粒度下的可编程反向偏置以及用于平衡工艺分布中的泄漏和性能的Smart-VID等电源管理功能。
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.