Portable, Flexible, and Scalable Soft Vector Processors
Portable, Flexible, and Scalable Soft Vector Processors
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便携式、灵活且可扩展的软矢量处理器
DOI：
10.1109/tvlsi.2011.2160463
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发表时间：
2012
影响因子：
2.8
通讯作者：
Jonathan Rose
中科院分区：
文献类型：
--
作者：
Peter Yiannacouras;J. Steffan;Jonathan Rose
现场编程的门阵列（FPGA）越来越多地用于实现嵌入式数字系统，但是，这样做的硬件设计是耗时和乏味的。可以通过使用微处理器来减少系统中的计算，可以减少硬件设计的量。通常，该微处理器是使用FPGA可重编程面料作为软处理器实现的，该处理器目前具有简单的体系结构和适度的性能。我们的目标是扩展现有软处理器的性能，从而将其适合性扩展到更批判的计算。为此，我们提出了使用矢量扩展的扩展软处理器，以利用许多嵌入式内核中发现的丰富数据并行性。这样的软矢量处理器可以比单核快得多地执行这些内核，从而减少了对硬件实现的需求。我们通过对矢量扩展软处理器体系结构（VESPA）进行实验，可以观察到这种提高的执行速度，该矢量是在实际FPGA硬件上设计，实现和评估的。 VESPA被证明可以有效地扩展性能高达32条车道，同时提供了实质性的建筑灵活性来创建精细的设计空间。借助这些特征和跨FPGA设备的可移植性，软矢量处理器可以提供精确的拟合体系结构，可以通过自定义的FPGA硬件设计有效，更容易地实现数据并行工作负载。
Field-programmable gate arrays (FPGAs) are increasingly used to implement embedded digital systems, however, the hardware design necessary to do so is time-consuming and tedious. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor which presently have simple architectures and moderate performance. Our goal is to scale the performance of existing soft processors hence expanding their suitability to more critical computation. To this end we propose extending soft processors with vector extensions to exploit the abundant data parallelism found in many embedded kernels. Such a soft vector processor can execute these kernels much faster than a single-core hence reducing the need for hardware implementations. We observe this improved execution speed through experimentation with vector extended soft processor architecture (VESPA) which is designed, implemented, and evaluated on real FPGA hardware. VESPA is shown to effectively scale performance up to 32 lanes, while providing substantial architectural flexibility to create a fine-grained design space. With these characteristics, and portability across FPGA devices, soft vector processors can provide exact-fit architectures which can efficiently and more easily implement data parallel workloads over custom FPGA hardware design.