Tools and techniques for evaluating reliability trade-offs for NANO-architectures
Tools and techniques for evaluating reliability trade-offs for NANO-architectures
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用于评估 NANO 架构可靠性权衡的工具和技术
DOI：
10.1007/1-4020-8068-9_6
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
S. Shukla
中科院分区：
文献类型：
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作者：
D. Bhaduri;S. Shukla
当我们缩小到纳米制造技术时，以量子、分子和其他计算模型形式的纳米计算正在激增。根据许多专家的说法，预计纳米级器件和互连将在基板中引入前所未有的缺陷，而架构设计需要适应这种规模固有的不确定性。这种考虑促使人们寻找基于冗余的容错设计的新架构范例。然而，冗余并不总是可靠性问题的解决方案，通常过多或过少的冗余都可能导致可靠性的缺乏。关键的挑战在于确定设计缺陷容忍度的粒度，以及实现特定可靠性级别的冗余级别。各种形式的冗余，如NAND多路复用，三模冗余（TMR），级联三模冗余（CTMR）已经在容错文献中被考虑。此外，冗余还应用于不同粒度级别，如门级、逻辑块级、逻辑函数级、单元级等。用于评估这种可靠性与冗余权衡的分析概率模型容易出错，而且很麻烦。在本章中，我们讨论了不同的分析和自动化方法，这些方法可以评估组合逻辑块的可靠性度量，并可用于分析不同架构配置的可靠性和冗余之间的权衡。我们还说明了我们的可靠性分析工具的有效性，指出了某些反直觉的异常情况，这些异常情况可以由设计人员通过自动化轻松获得，从而为容错设计决策提供了更好的见解。我们预见，这些工具将有助于进一步研究和教学兴趣在这一领域，加快可靠性分析过程，提高准确性建立可靠性冗余权衡点。
Nano-computing in the form of quantum, molecular and other computing models is proliferating as we scale down to nano-meter fabrication technologies. According to many experts, it is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause lack of reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Various forms of redundancy such as NAND multiplexing, Triple Modular Redundancy (TMR), Cascaded Triple Modular Redundancy (CTMR) have been considered in the fault-tolerance literature. Also, redundancy has been applied at different levels of granularity, such as gate level, logic block level, logic function level, unit level etc. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome. In this chapter, we discuss different analytical and automation methodologies that can evaluate the reliability measures of combinational logic blocks, and can be used to analyze trade-offs between reliability and redundancy for different architectural configurations. We also illustrate the effectiveness of our reliability analysis tools pointing out certain anomalies which are counter intuitive and can be obtained easily by designers through automation, thereby providing better insight into defect-tolerant design decisions. We foresee that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points.