High-quality SiN x /p-GaN metal-insulator-semiconductor interface with low-density trap states
High-quality SiN x /p-GaN metal-insulator-semiconductor interface with low-density trap states
复制标题
具有低密度陷阱态的高质量 SiN x /p-GaN 金属-绝缘体-半导体界面
DOI：
10.1088/1361-6463/aaf5ba
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
Sang Liwen
中科院分区：
文献类型：
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作者：
Ren Bing;Liao Meiyong;Sumiya Masatomo;Su Jin;Liu Xinke;Koide Yasuo;Sang Liwen
我们报道了一种高质量的p-GaN金属-绝缘体-半导体（MIS）电容器，具有尖锐的界面形态和最低的界面陷阱密度，使用SiN x作为栅介质层。透射电子显微镜和X射线光电子能谱（XPS）分析表明，高质量的界面形态与有效的去除碳和氧杂质。与Al 2 O 3、SiO 2和CaF 2/p-GaN金属氧化物半导体（MOS）或MIS电容器的界面特性相比，SiN x/p-GaN的电容-电压测量结果表明，经过两步表面预处理后，其电滞后可以忽略不计，导致最低的陷阱电荷密度为5× 10 10 cm− 2。在Et-Ev = 0.2-0.45 eV处，界面态密度分布也降低到约1-2× 1012 cm− 2· eV− 1，在价带边缘附近，界面态密度分布降低到3-5× 1012 cm− 2· eV− 1。通过有效的表面处理和无氧淀积工艺抑制了Al 2 O3/p-GaN MOS界面上常见的Mg-Ga-O界面无序层，从而获得了高质量的MIS界面。
We report on a high-quality p-GaN metal-insulator-semiconductor (MIS) capacitors with sharp interface morphology and the lowest interface trap density by using SiN x as the gate dielectric layer. Transmission electron microscopy and x-ray photoelectron spectroscopy (XPS) analysis revealed a high-quality interface morphology with the effective removal of carbon and oxygen impurities. Better than the interface properties of Al 2 O 3, SiO 2, and CaF 2/p-GaN metal-oxide-semiconductor (MOS) or MIS capacitors, the capacitance-voltage measurements of SiN x/p-GaN showed negligible electrical hysteresis after a two-step surface pre-treatment, leading to the lowest trapped charge density of 5× 10 10 cm− 2. The interface state density distribution was also reduced to be~ 1–2× 10 12 cm− 2· eV− 1 at E t–E v= 0.2–0.45 eV and 3–5× 10 12 cm− 2· eV− 1 near the valance-band edge after the treatments. The achievement of the high-quality MIS interface was attributed to the suppression of the Mg-Ga-O interfacial disordered layer by the effective surface treatments and oxygen-free deposition process, which was usually observed at Al 2 O 3/p-GaN MOS interface.