Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors
Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors
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DOI:
10.1109/ted.2016.2601218
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发表时间:
2016-08
影响因子:
3.1
通讯作者:
Meng Zhang;Zhihe Xia;Wei Zhou;Rongsheng Chen;M. Wong;H. Kwok
中科院分区:
文献类型:
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作者:
Meng Zhang;Zhihe Xia;Wei Zhou;Rongsheng Chen;M. Wong;H. Kwok
In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-hlm transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time (tf). A faster tf brings a larger ON-current (ION) increase in the first stage and a larger ION decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to ION increase in the hrst stage and ION decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger ION increase in the hrst stage in BG poly-Si TFTs is attributed to the enhanced vertical electric held in the channel near the gate oxide, while the much smaller ION decrease in the second stage is attributed to lateral electric held reduction caused by the sharing of the held across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the hrst-stage degradation on the second-stage degradation is also clarified.