Reconfigurable Asynchronous Logic
Reconfigurable Asynchronous Logic
复制标题
可重构异步逻辑
DOI：
10.1109/cicc.2006.320939
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
R. Manohar
中科院分区：
文献类型：
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作者：
R. Manohar
将异步逻辑映射到灵活的底物的挑战包括在电路级灵活性，映射复杂性和逻辑开销之间建立平衡。我们已经开发了可重构的数据流架构来解决这些挑战，还创建了将设计映射到架构所需的必要综合流。该体系结构利用了异步逻辑的一些独特功能，并达到了一个大大超过以前的异步FPGA的性能
Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuit-level flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs