A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
复制标题
用于探索具有异构互连结构的 3D FPGA 的新颖框架
DOI：
10.1145/2133352.2133356
复制
发表时间：
2012
期刊：
影响因子：
--
通讯作者：
D. Soudris
中科院分区：
文献类型：
--
作者：
K. Siozios;V. Pavlidis;D. Soudris
异质互连结构是设计3-D现场可编程门阵列的一种有用方法。提出了一种在不同三维制造工艺下研究三维现场可编程门阵列异质互连方案的方法。在基准电路上的应用表明，与2-D现场可编程门阵列相比，该方法在延迟、功耗和总布线长度方面分别提高了约41%、32%和36%。这些改进是对减少层间连接数量的补充。层间连接越少，收益就越高。提出了一个面积模型来评估这一权衡。结果表明，异质3DFPGA与同质3DFPGA相比，所需面积减少37%。因此，异质FPGA可以表现出更高的制造成品率。还开发了一个设计工具集来支持对所提出的3-D现场可编程门阵列的各种性能指标的设计和探索。
A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the proposed methodology on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length of approximately 41%, 32%, and 36%, respectively, as compared to 2-D FPGAs. These improvements are additional to reducing the number of interlayer connections. The fewer interlayer connections are traded off for a higher yield. An area model to evaluate this trade-off is presented. Results indicate that a heterogeneous 3-D FPGA requires 37% less area as compared to a homogeneous 3-D FPGA. Consequently, the heterogeneous FPGAs can exhibit a higher manufacturing yield. A design toolset is also developed to support the design and exploration of various performance metrics for the proposed 3-D FPGAs.