On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities
On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities
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路线图末端的片上互连网络：限制和纳米技术机遇
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
J.D. Memdl
中科院分区：
文献类型：
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作者：
A. Naeemi;A. barvan;J.D. Memdl
单壁和多壁碳纳米管的物理模型。这些模型被用来量化的性能增强，他们可以提供潜在的，如果用作GSI芯片中的互连。对于较短的长度，单层SWCN互连可以将电容降低50%，而对于较长的长度，SWCN束可以将电导率提高高达100%。如果MWCN的长度大于约7 μ m的临界长度，则MWCN的电导率随直径而增加，否则随直径而减小
Physical models are presented for single- and multi-wall carbon nanotubes. The models are used to quantify the performance enhancements that they can potentially offer if used as interconnects in GSI chips. For short lengths, mono-layer SWCN interconnects can lower capacitance by 50% whereas for long lengths SWCN-bundles can improve conductivity up to 100%. Conductivity of MWCNs increases with diameter if they are longer than a critical length of about 7 mum and decreases otherwise