Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes
Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes
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DOI：
10.1109/tr.2022.3216014
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发表时间：
2023-06
影响因子：
5.9
通讯作者：
Alvaro Cintas-Canto;Mehran Mozaffari Kermani;R. Azarderakhsh
中科院分区：
文献类型：
--
作者：
Alvaro Cintas-Canto;Mehran Mozaffari Kermani;R. Azarderakhsh
GF（2^{m}）上的有限域算术运算广泛应用于密码学、编码理论、纠错码和数字信号处理等关键领域。有限域反演是其他广泛使用的操作中最耗时的操作，并且需要大的占地面积以及要执行的功率/能量。为了降低这种复杂性，伊藤-Tsujii算法（ITA）在文献中得到了突出的关注，然而，使用ITA的实现仍然容易受到自然的超大规模集成缺陷的影响。为了克服检测自然引起的故障，在这样的建设的挑战，第一次，我们提出了错误检测计划的基础上汉明码的架构执行有限域反演使用ITA算法在$\text{GF}（2^{m}）$与多项式的基础。此外，CRC导向的错误检测计划的反演$\text{GF}（2^{m}）$与正常的基础也进行了研究，并提出了新的方法来保护他们。在这篇文章中，一般配方提供沿着不同的案例研究，以显示我们的计划的可行性与任何有限的字段大小。此外，现场可编程门阵列（FPGA）的实现是在两个Xilinx FPGA系列，即，Kintex UltraScale+和Xilinx Virtex-7 UltraScale+，以验证错误检测架构为提供可靠性而增加的开销是否适用于深度受限的嵌入式系统。
Finite field arithmetic operations over $\text{GF}(2^{m})$ are widely used in critical applications, such as cryptography, coding theory, error-correcting codes, and digital signal processing. Finite field inversions are the most time-consuming operations among other widely-used ones and require a large footprint as well as power/energy to be performed. To reduce such complexity, the Itoh–Tsujii algorithm (ITA) has received prominent attention in the literature; however, implementations using ITA are still vulnerable to natural very-large-scale integration defects. To overcome the challenge of detecting naturally-induced faults in such constructions, for the first time, we propose error detection schemes based on Hamming codes for architectures performing finite field inversions using the ITA algorithm over $\text{GF}(2^{m})$ with polynomial basis. Additionally, CRC-oriented error detection schemes for inversions in $\text{GF}(2^{m})$ with normal basis are also studied and new approaches to protect them are presented. In this article, general formulations are provided along with different case studies to show the feasibility of our schemes with any finite field size. Moreover, field-programmable gate array (FPGA) implementations are performed on two Xilinx FPGA families, i.e., Kintex UltraScale+ and Xilinx Virtex-7 UltraScale+, to verify that the overheads added by the error detection architectures to provide reliability are suitable for deeply-constrained embedded systems.