The Raw Compiler Project
The Raw Compiler Project
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原始编译器项目
DOI：
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发表时间：
1999
期刊：
影响因子：
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通讯作者：
M. Taylor
中科院分区：
文献类型：
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作者：
A. Agarwal;Saman P. Amarasinghe;R. Barua;M. Frank;W. Lee;Vivek Sarkar;D. Srikrishna;M. Taylor
今天的编译器能够推断程序并行性的详细信息并分析整个程序的行为。然而，由指令集体系结构（ISA）定义的编译器和处理器之间的传统接口无法将编译器的大部分知识传递给处理器。现代处理器（如superscalars）采用的方法是将纯运行时算法合并到其硬件中，以执行分析和优化，例如检测指令级并行性。然而，这些复杂的硬件实现只能利用编译器可用的并行性信息的一小部分。麻省理工学院开发的Raw架构旨在通过完全暴露硬件并将硬件的控制完全委托给软件系统来最大限度地利用编译器。Raw微处理器是一组简单的类似risc的处理器模块，与高速二维网格网络相连，不为传统微处理器中的任何复杂算法提供硬件实现。相反，编译器和运行时软件系统完全编排了原始硬件资源，并且它们实现了针对每个单独应用程序的需要进行的运行时分析和优化。这种新颖的方法为Raw编译器和运行时系统提供了许多机会和挑战。
Compilers today are capable of inferring detailed information about program parallelism and analyzing whole-program behavior. However, the traditional interface between the compiler and the processor, as defined by the instruction set architecture (ISA), is unable to communicate much of the compiler knowledge to the processor. The approach taken by modern processors such as superscalars is to incorporate purely run-time algorithms in their hardware to perform analyses and optimizations such as detection of instruction-level parallelism. However, these complex hardware implementations can only exploit a small fraction of the parallelism information available to the compiler. The Raw architecture developed at MIT aims to maximally utilize the compiler by fully exposing the hardware and by delegating the hardware’s control completely to the software system. The Raw microprocessor, a set of simple RISC-like processor tiles interconnected with a high-speed 2D mesh network, does not provide hardware implementations for any of the complex algorithms found in conventional microprocessors. Instead, the compiler and the run-time software system fully orchestrate the Raw hardware resources, and they implement run-time analyses and optimizations tailored to the need of each individual application. This novel approach provides many opportunities and challenges for the Raw compiler and run-time system.