Power-Efficient Hardware Architecture of K-Means Clustering With Bayesian-Information-Criterion Processor for Multimedia Processing Applications
Power-Efficient Hardware Architecture of K-Means Clustering With Bayesian-Information-Criterion Processor for Multimedia Processing Applications
复制标题
DOI：
10.1109/jetcas.2011.2165231
复制
发表时间：
2011-10
影响因子：
4.6
通讯作者：
Tse-Wei Chen;Chih-Hao Sun;Hsiao-Hang Su;Shao-Yi Chien;Daisuke Deguchi;I. Ide;H. Murase
中科院分区：
文献类型：
--
作者：
Tse-Wei Chen;Chih-Hao Sun;Hsiao-Hang Su;Shao-Yi Chien;Daisuke Deguchi;I. Ide;H. Murase
提出了一种节能的K-Means硬件架构，可以在聚类过程中自动估计簇的数量。这项工作的贡献包括两个主要方面。一是在硬件上集成分层数据采样，加快聚类速度;第二个是“贝叶斯信息准则（BIC）处理器”的发展，估计聚类的K均值的数量。在简化BIC计算的基础上设计了BIC处理器的结构，并对对数函数的精度进行了分析。实验表明，该结构可以应用于不同的多媒体应用，如运动分割和边缘自适应降噪。此外，硬件的门数为51 K与90纳米互补金属氧化物半导体技术。它还表明，这项工作可以实现高效率相比，GPU，和功耗的规模以及集群的数量和维数。当工作频率为233 MHz时，不同模式下的功耗范围为10.72至12.95 mW。
A power-efficient K-Means hardware architecture that can automatically estimate the number of clusters in the clustering process is proposed. The contributions of this work include two main aspects. The first is the integration of the hierarchical data sampling in the hardware to accelerate the clustering speed. The second is the development of the “Bayesian-Information-Criterion (BIC) Processor” to estimate the number of clusters of K-Means. The architecture of the “BIC Processor” is designed based on the simplification of the BIC computations, and the precision of the logarithm function is also analyzed. The experiments show that the proposed architecture can be employed in different multimedia applications, such as motion segmentation and edge-adaptive noise reduction. Besides, the gate count of the hardware is 51 K with the 90-nm complimentary metal-oxide-semiconductor technology. It is also shown that this work can achieve high efficiency compared with a GPU, and the power consumption scales well with the number of clusters and the number of dimensions. The power consumption ranges between 10.72 and 12.95 mW in different modes when the operating frequency is 233 MHz.