Rapid Solder Interconnect Fatigue Life Test Methodology for Predicting Thermomechanical Reliability

Rapid Solder Interconnect Fatigue Life Test Methodology for Predicting Thermomechanical Reliability
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用于预测热机械可靠性的快速焊料互连疲劳寿命测试方法

DOI:
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发表时间:
2018
影响因子:
2
通讯作者:
D. Huitink
D. Huitink
中科院分区:
工程技术3区
文献类型:
--
作者:
Cody J. Marbut;Mahsa Montazeri;D. Huitink

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设计了一种快速可靠性测试方法,用于模拟倒装芯片器件在温度循环中由热膨胀引起的剪切引起的机械应力,以便在典型环境测试中从热效应中去卷积剪切应力。使用根据弹簧偏转的受控力施加,建立了一个测试台,以在等温条件下机械地向倒装芯片器件中的焊料互连施加剪切应力。使用摩擦计循环施加剪切应力,以模拟在操作或加速测试中的热循环期间在器件的互连中引起的机械应力。在剪切的机械应用中,可以精确地控制载荷和循环速率的控制,同时监控观察裂纹扩展和损伤的关键因素。在这样做的过程中,这种新颖的方法引入了将剪切应力和塑性功累积(损伤)与通用器械中的疲劳寿命直接相关的能力,利用有限元模型以及数据采集的帮助。使用所获得的相关性,寿命预测,通过早期阶段的设计分析是可能的,铺平了道路的先验优化设计倒装芯片器件的热机械可靠性。本文提出的方法创造了消除对多种电子设备设计/配置进行昂贵的寿命测试的机会,同时还加快了新材料或工艺相关的可靠性影响所需的任何数据收集。
A rapid reliability test methodology was devised for simulating mechanical stresses induced from thermal expansion induced shear in temperature cycling of flip-chip devices in order to de-convolute shear stress from thermal effects in typical environmental tests. Using controlled force application according to spring deflection, a test stand was created to mechanically apply shear stress to solder interconnects in flip chip devices at isothermal conditions. The shear stress was applied cyclically using a tribometer to simulate the mechanical stresses induced in the interconnects of a device during a thermal cycle while in operation or accelerated testing. In the mechanical application of shear, the control of loading and cyclic rate can be precisely controlled while monitoring key factors for observing crack propagation and damage. In doing so, this novel approach introduces the ability to directly correlate shear stress and plastic work accumulation (damage) to fatigue life in a generic device, utilizing help from finite element models alongside data acquisition. Using the obtained correlations, lifetime predictions through early stage design analysis are possible, paving the way for a-priori optimized design for thermomechanical reliability in flip-chip devices. The methodology presented herein creates the opportunity to eliminate costly lifetime testing on multiple electronic device designs/configurations, while also expediting any data collection needed for new materials or process related impacts to reliability.