A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping
A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping
复制标题
小数 N MASH2-k FDC 锁相环架构可实现高阶量化噪声整形
DOI：
10.1049/ell2.12436
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发表时间：
2022
期刊：
影响因子：
--
通讯作者：
and T. Iizuka
中科院分区：
文献类型：
--
作者：
R. Iwashita;Z.Xu;M. Osada;and T. Iizuka
传统FDC锁相环（PLL）的量化噪声贡献仍然很高，因为它只有二阶噪声整形能力。提出了一种MASH 2-k FDC PLL架构，可实现（k+ 2）阶噪声整形，以实现更灵活的环路设计优化和更宽的环路带宽，从而抑制数控振荡器的噪声。推导了线性环路模型，并分析了噪声的贡献。所提出的锁相环进行了评估与行为仿真的结果是一致的分析。结果还表明，与传统的锁相环相比，所提出的锁相环具有更低的相位噪声。
The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling (k+ 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally controlled oscillator is proposed. The linear loop model is derived, and the noise contributions are analysed. The proposed PLL is evaluated with behavioural simulation whose results are consistent with those of the analysis. The results also suggest a lower phase noise of the proposed PLL compared with the conventional one.