High performance 600 V smart power technology based on thin layer silicon-on-insulator

High performance 600 V smart power technology based on thin layer silicon-on-insulator
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DOI：
10.1109/ispsd.1997.601428
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发表时间：
1997-05
期刊：
Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's
影响因子：
--
通讯作者：
T. Letavic;E. Arnold;M. Simpson;R. Aquino;H. Bhimnathwala;R. Egloff;A. Emmerik;S. Wong;
T. Letavic;E. Arnold;M. Simpson;R. Aquino;H. Bhimnathwala;R. Egloff;A. Emmerik;S. Wong;
中科院分区：
其他
文献类型：
--
作者：
T. Letavic;E. Arnold;M. Simpson;R. Aquino;H. Bhimnathwala;R. Egloff;A. Emmerik;S. Wong;

文献摘要

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提出了一种高性能600 V智能功率技术，该技术将新型横向双扩散MOS晶体管（LDMOS）与BiCMOS工艺流程相结合，用于在绝缘体上硅（BSOI）衬底上构建功率集成电路。所有的有源和无源器件结构已被优化用于在厚度小于1.5 μ m/s的BSOI层上制造，其中掩埋氧化物层的厚度在2.0 μ m/s至3.0 μ m/s的范围内。由于使用了薄SOI有源器件层，所以完全的电介质隔离处理是直接的。对于给定的击穿电压，高压器件的双场板设计导致比导通电阻相对于常规LDMOS结构减小至少两倍。
A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 /spl mu/m-thick, with buried oxide layers in the range of 2.0 to 3.0 /spl mu/m-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage.