B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
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B-Fetch：芯片多处理器的分支预测定向预取
DOI：
10.1109/micro.2014.29
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Daniel A. Jiménez
中科院分区：
文献类型：
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作者：
David Kadjo;Jinchun Kim;Prabal Sharma;Reena Panda;Paul V. Gratz;Daniel A. Jiménez
几十年来，缓解“内存墙”的主要工具一直是大型缓存层次结构和数据预取器。这两种方法在现代芯片多处理器（CMP）设计中变得更具挑战性。增加最后一级缓存（LLC）的大小会导致每瓦性能的收益递减，考虑到VLSI功耗缩放趋势，这种方法变得难以证明。这些趋势也影响了预取器的硬件预算。此外，在运行多个并发进程的CMP的上下文中，预取准确性对于防止缓存污染影响至关重要。这些关注点需要一个轻量级的高精度的预取。现有的数据预取器通常可以被分类为低开销和低准确度（Next-n、Stride等）。或高开销和高精度（STeMS、ISB）。提出了一种基于分支预测和有效地址值推测的数据预取器B-Fetch。B-Fetch利用控制流预测来生成执行应用程序的预期未来路径。然后，它根据过去寄存器转换的历史，推测性地计算沿着该路径的加载指令的有效地址沿着。使用周期精确模拟器进行的详细模拟显示，单线程工作负载的几何平均加速比为23.4%，多应用程序工作负载的几何平均加速比为28.6%。我们发现，B-Fetch优于现有的“一流的”轻量级预取下单线程和多编程工作负载的9%，平均存储开销减少65%。
For decades, the primary tools in alleviating the "Memory Wall" have been large cache hierarchies and dataprefetchers. Both approaches, become more challenging in modern, Chip-multiprocessor (CMP) design. Increasing the last-level cache (LLC) size yields diminishing returns in terms of performance per Watt, given VLSI power scaling trends, this approach becomes hard to justify. These trends also impact hardware budgets for prefetchers. Moreover, in the context of CMPs running multiple concurrent processes, prefetching accuracy is critical to prevent cache pollution effects. These concerns point to the need for a light-weight prefetcher with high accuracy. Existing data prefetchers may generally be classified as low-overhead and low accuracy (Next-n, Stride, etc.) or high-overhead and high accuracy (STeMS, ISB). Wepropose B-Fetch: a data prefetcher driven by branch prediction and effective address value speculation. B-Fetch leverages control flow prediction to generate an expected future path of the executing application. It then speculatively computes the effective address of the load instructions along that path based upon a history of past register transformations. Detailed simulation using a cycle accurate simulator shows a geometric mean speedup of 23.4% for single-threaded workloads, improving to 28.6% for multi-application workloads over a baseline system without prefetching. We find that B-Fetch outperforms an existing "best-of-class" light-weight prefetcher under single-threaded and multi programmed workloads by 9% on average, with 65% less storage overhead.